Freescale Semiconductor /MKW24D5 /SIM /CLKDIV1

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Interpret as CLKDIV1

31282724232019161512118743000000000000000000000000000000000000000000 (0000)OUTDIV40 (0000)OUTDIV20 (0000)OUTDIV1

OUTDIV4=0000, OUTDIV1=0000, OUTDIV2=0000

Description

System Clock Divider Register 1

Fields

OUTDIV4

Clock 4 output divider value

0 (0000): Divide-by-1.

1 (0001): Divide-by-2.

2 (0010): Divide-by-3.

3 (0011): Divide-by-4.

4 (0100): Divide-by-5.

5 (0101): Divide-by-6.

6 (0110): Divide-by-7.

7 (0111): Divide-by-8.

8 (1000): Divide-by-9.

9 (1001): Divide-by-10.

10 (1010): Divide-by-11.

11 (1011): Divide-by-12.

12 (1100): Divide-by-13.

13 (1101): Divide-by-14.

14 (1110): Divide-by-15.

15 (1111): Divide-by-16.

OUTDIV2

Clock 2 output divider value

0 (0000): Divide-by-1.

1 (0001): Divide-by-2.

2 (0010): Divide-by-3.

3 (0011): Divide-by-4.

4 (0100): Divide-by-5.

5 (0101): Divide-by-6.

6 (0110): Divide-by-7.

7 (0111): Divide-by-8.

8 (1000): Divide-by-9.

9 (1001): Divide-by-10.

10 (1010): Divide-by-11.

11 (1011): Divide-by-12.

12 (1100): Divide-by-13.

13 (1101): Divide-by-14.

14 (1110): Divide-by-15.

15 (1111): Divide-by-16.

OUTDIV1

Clock 1 output divider value

0 (0000): Divide-by-1.

1 (0001): Divide-by-2.

2 (0010): Divide-by-3.

3 (0011): Divide-by-4.

4 (0100): Divide-by-5.

5 (0101): Divide-by-6.

6 (0110): Divide-by-7.

7 (0111): Divide-by-8.

8 (1000): Divide-by-9.

9 (1001): Divide-by-10.

10 (1010): Divide-by-11.

11 (1011): Divide-by-12.

12 (1100): Divide-by-13.

13 (1101): Divide-by-14.

14 (1110): Divide-by-15.

15 (1111): Divide-by-16.

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